Large modern integrated circuit (IC) designs are increasingly created by assembling a number of previously-designed circuit portions, which is done to reduce design turnaround times. Schematic and layout information for such circuit portions may be exchanged or licensed as design intellectual property (IP).
The requirements and demands on ICs have increased steadily over the past decade. As the IC's have become more complicated, their analysis and optimization has also become more complicated. Demands on the software and hardware used for analysis and optimization of complicated IC's may exceed their capabilities. To this end, it would be beneficial to formulate methods and systems that simplify the analysis and optimization of large and/or complicated ICs.
One result of the more stringent requirements and demands on the performance of ICs is the use of parallel chip architectures. Parallel architectures provide multiple instances of the same design IP integrated onto a single circuit die, or onto multiple dies in a single chip package. One example of a parallel architecture is a multi-core processor.
A multi-core processor is a single computing component with two or more independent actual central processing units (called “cores”), which are the units that read and execute program instructions. Multicore processors may have two cores, four cores, or more. Multi-core processors are widely used across many application domains including general-purpose, embedded, network, digital signal processing (DSP), and graphics.
When a single IC includes multiple instances of the same design IP, one instance may be referred to as the master while additional instances may be referred to as clones. Master-clone optimization has been a challenge in hierarchical design flow due to a number of factors: 1. The traditional timing budget approach leads to inaccurate and static interface timing info, which may degrade optimization quality of results (QoR); 2. Newly developed methodologies to account for accurate interface timing such as Reverse Interface Logic Model (ReverseILM) produce different external timing and physical context for each master-clone instance, which may lead to difficult iterative master-clone sync up.